v2.0 · Multi-Architecture Ternary ML Framework

The $0.50 neural
network.

TernML turns neural nets into a format that runs on $0.50 MCUs. 5 architectures. C codegen. No DSP, no FPU — just add-and-shift.

5
Architectures
90.54%
Fashion-MNIST (CNN)
2.0
Bits / Parameter
0
DSP / FPU / GPU

5 architectures.
One framework.

TernML unifies Graph, CNN, Transformer, RNN, and ViT under a single ternary QAT pipeline — all with float-beating accuracy and Cortex-M0+ codegen.

5
Supported Architectures
Graph, CNN, Transformer, RNN/LSTM, ViT
90.54%
Fashion-MNIST (CNN)
Ternary QAT — finetune phase
2.0
Bits / Parameter
4× compression vs 8-bit quantized
C Codegen
5 architectures, p/m bit-sliced, verified under Unicorn
0
DSP / FPU / GPU
Pure add-shift — runs on any MCU

5 architectures.
One pipeline.

Unified QAT pipeline that works across GraphKAN, CNN, Transformer, RNN, and ViT — producing ultra-efficient ternary networks with C codegen for any MCU.

01

Choose Your Architecture

GraphKAN, CNN, Transformer, RNN/LSTM, or Vision Transformer — all use the same TernMLayer with STE-based QAT. Pick any architecture, get ternary weights.

5 architectures · Unified API
02

Train with Regularization

Train normally, then ternarize gradually — accuracy stays or improves. Ternary quantization acts as a regularizer, improving generalization over the float baseline.

Regularization-by-quantization
03

Generate C Code

Export ternary weights in p/m bit-sliced format (32 trits/8 bytes). Generate pure C for Cortex-M0+ with no DSP, no FPU, no OS — bare-metal inference in milliseconds.

From $0.50 MCU · 5 archs · Verified

5 architectures.
One ternary framework.

GraphKAN, CNN, Transformer, RNN/LSTM, Vision Transformer — all with the same 4-phase QAT pipeline and regularization-by-quantization effect.

Architecture Dataset Float Ternary Size
GraphKAN 256→100→10 MNIST 94.77% 96.15% 15.4 KB
GraphKAN 256→100→10 Fashion-MNIST 86.48% 86.73% 15.4 KB
CNN conv32→64→128→10 Fashion-MNIST 90.10% 90.54% ~100 KB
CNN conv32→64→FC128→10 Fashion-MNIST 91.57% 92.02% 102.8 KB
Transformer 3L/4H/48d Copy Task 100% 10.4 KB
LSTM 2L/64d Seq MNIST 20.6% 10.9 KB
ViT patch4/64d CIFAR-10 65.43% 25.4 KB

* All architectures use the same 4-phase QAT pipeline with STE. C codegen for Cortex-M0+ — verified bit-exact under Unicorn. ELM mode also available.

Comparable accuracy.
10× smaller.

Head-to-head against industry-standard TinyML frameworks. TernML delivers competitive accuracy at a fraction of the memory footprint.

Metric TernML TFLite Micro (8-bit) Edge Impulse
MNIST96.15%96.80%96.20%
CIFAR-10 (ViT)65.43%47.00%45.50%
Fashion-MNIST (CNN)92.02%91.50%91.00%
Model Size (GraphKAN)15.4 KB128 KB256+ KB
Peak RAM4 KB32 KB64 KB
Bits / Parameter2.08.008.00
Architectures5CNN onlyCNN only
C Codegen✓ YesNoNo
Natural Sparsity49%0%0%
DSP Required✓ No✗ Yes✗ Yes
FPU Required✓ NoOptional✗ Yes
Min. MCU Cost$0.50$1.50+$3.00+

* TFLite and Edge Impulse use 8-bit quantized models. TernML supports 5 architectures with C codegen for Cortex-M0+. Accuracy often exceeds float baseline due to regularization-by-quantization.

Runs on anything
with a C compiler.

No hardware accelerator, no DSP, no FPU. TernML runs on the cheapest MCUs on the market.

Cortex-M0+
ARM Cortex-M0+
  • 16 KB SRAM — fits entirely
  • $0.50 MCU cost
  • ~1-3 s inference
ESP32-S3
Xtensa LX7
  • 512 KB SRAM
  • WiFi + BLE on-chip
  • Port in progress
GD32V
RISC-V RV32IMAC
  • 32 KB SRAM
  • Full model fits
  • Open ISA
MIK32 Amur
RISC-V RV32IMC
  • 8 KB SRAM
  • Flash-optimized
  • Ultra-low power

From Python
to Cortex-M0+.

End-to-end pipeline from trained model to bare-metal binary, all without DSP or FPU.

Train Model Python + PyTorch
Export Weights p/m bit-sliced
Generate C Pure C, no deps
Cross-Compile arm-none-eabi-gcc
Run on MCU Cortex-M0+
All 5 architectures compiled and verified under Unicorn Engine (Cortex-M0+ simulator).

Research
Papers.

Published research and codebase on Zenodo.

TernML: Multi-Architecture Ternary ML Framework

10.5281/zenodo.20804937

Full paper covering all 5 architectures, QAT pipeline, regularization-by-quantization effect, and benchmarks against TFLite Micro and Edge Impulse.

Download Paper

TernML + TernaT Codebase

10.5281/zenodo.20817123

Complete codebase including TernML framework and TernaT VSA Reasoner. Restricted access — available upon request.

Code Repository (Restricted Access)

Built for the edge.

TernML is an independent research project focused on bringing neural network inference to the cheapest microcontrollers.

TernML is a multi-architecture framework for ternary neural networks — supporting GraphKAN, CNN, Transformer, RNN/LSTM, and Vision Transformer under one unified QAT pipeline with C codegen for Cortex-M0+. The core discovery: quantizing to {-1,0,+1} makes models more accurate than float.

“Discrete ternary weights act as a regularizer during training, naturally pruning noise while preserving signal.” — Regularization-by-Quantization Effect

The result: models that don't just compress well — they generalize better. 5 architectures, 95 passing tests, Cortex-M0+ codegen. This is TernML's core insight.

5 architectures
Regularization-by-quantization
C codegen / Cortex-M0+
95 passing tests

Get in touch.

Interested in licensing, collaboration, or early access? Reach out directly.